1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a voltage generating circuit capable of increasing a current capacity according to an operation mode of a nonvolatile semiconductor memory device.
2. Description of the Related Art
Semiconductor memories are usually considered to be the most vital microelectronic component of digital logic system design, such as computers and microprocessor-based applications ranging from satellite to consumer electronics. Therefore, advances in the fabrication of semiconductor memories including process enhancements and technology developments through the scaling for higher densities and faster speeds help establish performance standards for other digital logic families.
Semiconductor memories are classified into volatile semiconductor memories and non-volatile semiconductor memories. In the volatile semiconductor memories, data are stored and can be read out as long as the power is applied, and are lost when the power is turned off. On the other hand, non-volatile memories such as a MROM (MASK ROM), a PROM (Programmable ROM), an EPROM (Erasable and Programmable ROM), and an EEPROM (Electrically Erasable and Programmable ROM) are capable of storing data even with the power turned off. Flash memories are widely used in computers and memory cards because of their capability to for electrically and collectively erase data of cells.
Flash memories are classified into NOR-type flash memories and NAND-type flash memories according to a connection structure of a cell and a bitline. The NOR-type flash memory has a structure wherein two or more cell transistors are connected to a bitline in parallel. In the NOR-type flash memory, data is stored using channel hot electron mechanism and erased using F-N tunneling mechanism. The NAND-type flash memory has a structure wherein more than two cell transistors are connected to a bitline in series. Data are stored and erased using F-N tunneling mechanism. The NOR-type flash memory can be easily adapted to high-speed and is disadvantageous in high-integration because of its high power consumption. The NAND-type flash memory is advantageous in high-integration because it uses less current than the NOR-type flash memory.
FIG. 1 is a cross-sectional view of a flash memory cell. The flash memory cell is comprised of source/drain regions 3 and 4 which are doped with N+ impurities and formed on a P-type semiconductor substrate 2 with a channel region interposed therebetween. The floating gate 6 is formed on the channel region with thin insulating layer 7 of 100 Å or less interposed therebetween on the channel region. A control gate 8 is formed on the floating gate 6 with an insulating layer 9 interposed therebetween. In order to apply voltages for programming, erasing, and reading, power supply terminals Vb, Vs, Vd, and Vg are respectively connected to the substrate 2, the source 3, the drain 4, and the control gate 8.
In general, flash memories are programmed by channel hot electron injection (CHE) where hot electrons are generated from the channel region adjacent to the drain region 4 and are injected to the floating gate 6. In order to program a cell by channel hot electron injection, a high voltage of about 10V is applied to a wordline (floating gate 6) of a selected cell, and a voltage (e.g., 4V˜6V) suitable for generating a hot electron is applied to a bitline (drain) of a selected cell. And, the source region 3 is grounded to the semiconductor substrate 2, or a negative bulk voltage is applied to the semiconductor substrate 2. In this case, the applied wordline voltage, bitline voltage, and bulk voltage are generated through a charge pump in a chip, respectively. If flash memory cells are programmed under the condition of the above voltage application, a negative charge is sufficiently accumulated in the floating gate 6. While a series of read out operations are carried out, the negative charge accumulated in floating gate 6 performs a function to enhance a threshold voltage of the programmed flash memory cell.
FIG. 2 is a waveform of a programming voltage of a conventional NOR-type flash memory device. In FIG. 2, a bitline voltage VBL applied to a drain of a selected cell and a bulk voltage VBulk applied to a substrate of a selected cell are shown, respectively. Where, a bitline voltage denoted by VPBL represents a pumping voltage generated from a bitline pump circuit, and a bitline voltage denoted by VBL represents a voltage actually applied to a bitline.
For programming of flash memories, a bitline current (or a programming current) above a predetermined level is required because a high voltage of about 4V to 6V is applied to the drain of the memory cell. In particular, during an accelerated programming operation in which a plurality of memory cells (e.g., four times as many memory cells as in a normal programming operation) are programmed at once, a required bitline current in a selected bitline is increased more and more. As a desired amount of bitline current is increased, a sub-current amount is also increased. As a result, a level of the bulk voltage VBulk is enhanced. Accordingly, there is a problem that a programming operation is not performed normally.
Typical method for increasing a bitline current amount is to enhance a level of a pumping voltage by adding the number of stages of a pump circuit. According to this method, a layout area occupied by the pump circuit is spread. Since the accelerated programming operation is performed in a factory circumstance so as to reduce a programming time of NOR-type flash memories, the pump circuit with increased layout area is useless in normal circumstances.
Therefore, there is an increasing demand for a method capable of providing a sufficient current capacity required during an accelerated programming operation without increasing a chip size.
Accordingly, it would be desirable to provide a voltage generating circuit capable of providing a current capacity required for an accelerated programming operation without increasing a chip size. It would also be desirable to provide a non-volatile semiconductor memory device including such a circuit. It would further be desirable to provide a voltage generating circuit capable of providing a high programming reliability and a non-volatile memory device including it.